(a) Field of the Invention
The present invention relates to a flat panel display and a drive method thereof, and more particularly, to a flat panel display with a large screen and high resolution and a drive method thereof.
(b) Description of the Related Art
There is an ever-increasing effort of research to improve existing flat panel displays and develop new flat panel display configurations. Flat panel displays include the widely used liquid crystal display; plasma display panels, which are emissive like CRTs and so have an excellent viewing angle and color performance; and electroluminescent displays, which have a significantly better refresh rate than the CRT.
Flat panel displays typically include a flat panel on which a matrix of cells formed between two glass substrates is arranged, a PCB module for driving the flat panel, and a case for protecting and integrating these elements. In the LCD, the cells are not realized through luminous elements but instead through shutter switches. Accordingly, a back light unit must be provided to the rear of the liquid crystal panel.
The PCB modules in flat panel displays receive and process R, G, B image data and synchronization signals, then provide image data, scanning signals, and timing control signals to the flat panel. Accordingly, the PCB module acts as a drive circuit to enable the flat panel to perform the normal display of computer images, television images, etc. The PCB module is realized through a plurality of PCBs and a plurality of flexible printed cables (FPCs), which are used for the transmission of signals between the PCBs.
FIG. 1 shows a schematic block diagram of a prior art flat panel display, and FIG. 2 shows a PCB module of FIG. 1. As shown in the drawings, a PCB module for driving a flat panel 40 at a relatively low resolution (e.g., the SVGA standard of 600 by 800 pixels) includes a main PCB 10 for receiving R, G, B image data and synchronization signals, and processing the data and signals using a timing controller, which is a FPGA (flat pin grid array) custom IC, and for processing the image data and various control signals in a manner suitable for the structure of the flat panel 40; a row driver PCB 20 to which there is attached a row driver IC TAB (tape automated bond) 90, the row driver PCB 20 supplying scanning signals to a row signal wire according to row driver control signals received from the main PCB 10; and a column driver PCB 30 to which there is attached a column driver IC TAB (tape automated bond) 100, the column driver PCB 30 receiving image data and control signals processed in the main PCB 10, and supplying the image data to the flat panel 40. Further, an FPC 70 is provided to transmit row driver control signals 50 and 51 generated by the main PCB 10 to the row driver PCB 20, and an FPC 80 is provided to transmit column driver control signals 60 and 61 generated by the main PCB 10 to the column driver PCB 30.
However, with reference to FIG. 3, when image signals are supplied to a column signal wire 120 of the flat panel 40, a control unit operates by receiving control signals generated in a timing controller T-con of the main PCB 10 of FIG. 1. A D/A converter and a buffer amp operate according to control signals of the control unit such that image signals corresponding to gray voltages (V0–V63) are output to the column signal wire 120. Accordingly, even with a sufficient current drive capacity of the D/A converter and buffer amp, a higher processing speed screen and a high-resolution display, such as UXGA (1200 by 1600), QXGA (2048 by 1536), and QSXGA (2560 by 2048) distorts and delays the signals, because the inherent resistance and stray capacity increase in the row signal wire and column signal wire 120. Therefore, the signal effectively received by the device that controls the optical performance is distorted and only a portion of the intended signal. Such problems cannot be easily compensated in a big screen and a high resolution display and are summarized below.
(1) Problems of Large Screen Size and Drive Signal Distortion
Currently produced flat panel displays employ virtually no drive technologies that can solve signal distortion. Currently, the display is designed to minimize the resistance of metal wiring, or to minimize stray capacity load stemming from structural characteristics or thin film materials that comprise pixels. This increases the effective load, which is actually used for image display, minimizing the signal distortion.
In conventional methods, it is difficult to reduce the wiring resistance to the desired level because of the material characteristics and the process limitations of the wiring material. On the other hand, development of the new wiring materials also requires technologies for the manufacturing processes. This also requires additional research and manufacturing equipment. Further, it is not possible to reduce stray capacity past a certain amount through changes in pixel structure because of necessary structural conditions that must be satisfied, as well as design and manufacturing limitations.
Because of such restrictions, it is difficult to realize a high resolution and a big screen display (an over 20-inch, UXGA standard display in the case of LCDs, and an ultra-large screen, high resolution display in the case of PDPs). Large screens commonly used these days also experience an inferior picture quality and a defective final product (beyond acceptable levels) as a result of signal distortion. Although pixel wiring short-circuit can be repaired, such signal delays and distortions cannot be repaired.
2) Compensation of Drive Signal Distortion in Prior Art
At present, there are no drive technologies that compensate for or otherwise solve the problem of drive signal distortion in flat panel displays. A big screen display that may suffer visible degradition of image quality, may employ a dual scan drive method. The dual scan drive method drives a screen by dividing the screen into two in a scanning direction. Another dual drive method may apply the same image signals simultaneously to the signal wires on both sides of the panel.
The dual scanning method requires a signal processing circuit to convert the conventional signal into dual scan type signals, since image signals of an image signal transmission unit of a computer, television, etc., are single scan type signals. Such a circuit requires a large-capacity graphic data memory. As the resolution increases, the memory requirement also increases substantially. Further, since in dual scanning the drive signals are applied on both sides of the flat panel with a time difference, it is necessary to supply data signals and control signals to both sides of signal wires. This complicates the structure of the flat panel display, which negatively affects production. Finally, the divided screen in the dual scan drive method may be perceptible to users, thereby deteriorating overall picture quality.
The dual drive method may not need a signal processing circuit to convert single scan signals into dual scan signals like in the dual scan method, but the need of simultaneously applying drive signals to the signal wires on both sides of the flat panel complicates overall structure. Further, although there is the advantage of circumventing errors caused by a short in the signal wires since identical image signals are supplied to both sides of the panel, drive time with an increased resolution are only minimally saved, since the flat panel is basically a single scan type.